14. Coprocessor 0
14.12 Exception Program Counter (14)
The Exception Program Counter (EPC)*1 is a read/write register that contains the address at which processing resumes after an exception has been serviced.
For synchronous exceptions, the EPC register contains either:
- the virtual address of the instruction that was the direct cause of the exception, or
- the virtual address of the immediately preceding branch or jump instruction (when the instruction is in a branch delay slot, and the Branch Delay bit in the Cause register is set).
The processor does not write to the EPC register when the EXL bit in the Status register is set to a 1.
Figure 14-14 shows the format of the EPC register.
Figure 14-14 EPC Register Format
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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